Two Day Seminar with Text

The “CMOS IC Layout – A Guide to Topological Chip Design” text and Seminar is designed to guide the attendee to an intermediate level understanding of the actual processes used in generating a topological layout for a CMOS integrated circuit.

To accomplish this, Mr. Bradbury, the author of the text, will walk the attendee through the major steps in the IC development flow, layout floor planning, converting Design Engineering’s logic diagrams into transistor schematics, cell layout, how to build and use a standard cell library, and interconnect techniques. This is followed by descriptions of the processes that follow the layout through to the finished product including layout verification and how a minimum area layout affects device yield. Additionally, throughout the seminar, designing in reliability is stressed and the consequences of not adhering to good layout practice are shown graphically with scanning electron microscope photos to carry home the point.

The instructor will also present the latest material on layout with respect to copper interconnect, analog design issues that need to be addressed during layout. And in the area of deep submicron technologies, there are new Front-End concerns such as poly density (poly photo issues) diffusion stress effects and gate critical dimension uniformity – all of which were not seriously considered in past technologies.

By completing the exercises provided in the seminar, the student will understand the major elements of an IC development flow and be able to draw hierarchical cell structures of medium complexity.

This two day seminar is especially well suited to any individual that plans to work within the semiconductor industry or any field that is related to this industry. This includes education where an electronic curriculum or support subject is taught. It is also a must for graduate and potential EEs who will be developing semiconductor devices along with Computer Science Engineers who write software used for circuit design simulation and verification, layout and layout verification, Reliability and Test Engineering organizations and Layout Engineer candidates.

Contact EduMediaDevelopment for the latest schedule or to book dates with the speaker.